With the increase in integration density in dynamic random access memory (DRAM) and a ferroelectric RAM (FRAM) devices, ferroelectric materials such as PZT ((Pb,Zr)TiO.sub.3) or BST ((Ba,Sr)TiO.sub.3) have typically been used as dielectric films in storage capacitors. Ferroelectric material has spontaneous polarization, in contrast to conventional oxide films such as silicon nitride film or tantalum pentoxide film, and generally has a high dielectric constant of several hundred to 1000.
The upper and lower electrodes of a ferroelectric capacitor are generally composed of Pt-group elements. The lower electrode of the ferroelectric capacitor is typically connected to a contact plug composed of polysilicon or tungsten, and the upper electrode thereof is typically connected to a metal interconnection layer composed of aluminum. However, platinum (Pt) composing the upper and lower electrodes reacts with aluminum and this reaction can degrade the polarization characteristics of the ferroelectric capacitor. To avoid this problem, a barrier layer is typically provided between the electrode of the ferroelectric capacitor and aluminum metal interconnection layer. Also, to enhance contact resistance in forming a metal interconnection, an ohmic layer such as a Ti layer is interposed between the barrier layer and the upper electrode.
Hereinbelow, a structure of a semiconductor device having a conventional ferroelectric capacitor therein will be described with reference to FIG. 1. FIG. 1 is a sectional view for explaining metal interconnections in a cell array region and a peripheral circuit region. As shown in FIG. 1, in the cell array region there are provided a transistor including a field oxide film 2, source and drain regions 3 and 5 and a gate electrode 7 functioning as a word line, and a bit line 11 on a semiconductor substrate 1. A first interlayer dielectric (ILD) 13 and a second ILD 15 each having a storage contact hole are sequentially deposited over the transistor. A tungsten plug 17 is formed to fill the storage contact hole, and a lower electrode 19, a ferroelectric film 21 and an upper electrode 23 are sequentially formed on the tungsten plug 17 to provide the ferroelectric capacitor. A diffusion preventing film 24 is provided on the top and sides of the ferroelectric capacitor. A first intermetal dielectric (IMD) 27 and a second IMD 29 having via holes therein are sequentially formed over the ferroelectric capacitor. A second metal interconnection 31 is formed to fill the via holes. A Ti layer 25 is formed on the ferroelectric capacitor as an ohmic layer. A TiN layer 33 is interposed over the ohmic layer as a barrier layer. Thus, a Ti/TiN layer is interposed between the upper electrode 23 of the capacitor and the second metal interconnection 31.
Referring still to FIG. 1, in the peripheral circuit region adjacent to the cell array region, gate electrodes 7 and 9 and a bit line 11 are formed on the semiconductor substrate 1 on which the field oxide film 2 is formed. A first ILD 13, a second ILD 15 and a first IMD 27 each having a contact hole, are sequentially formed thereon. A first metal interconnection is formed through the contact hole. It is understood from FIG. 1 that the step height of the contact hole in the peripheral circuit region may be large, for example, about 1.5 .mu.m. If the step height is increased to such an extent, a void may be produced in the contact hole when filling the same with metal. A second IMD 29 having a via hole is formed over the first metal interconnection 35, and a second metal interconnection 31 is filled in the via hole to then be connected to a predetermined portion of the first metal interconnection 35. At this time, in order to improve contact resistance between metals, a Ti layer 25 as an ohmic layer is interposed therebetween. Also, a TiN layer 33 is interposed, over the ohmic layer, as a barrier layer.
As seen from FIG. 1, each via hole is formed in the cell array region and the peripheral circuit region after forming the first metal interconnection 35 and the second IMD 29. At this time, the portion where the via hole is formed extends opposite upper electrode 23 of the ferroelectric capacitor in the cell array region, and extends opposite the first metal interconnection 35 in the peripheral circuit region. The second metal interconnection 31 composed of aluminum is deposited in the via holes. Before the second metal interconnection 31 is deposited in the via holes, the Ti layer 25 as the ohmic layer and the TiN layer 33 as the barrier layer are deposited on the bottoms thereof. Therefore, the bottom of the via hole will have a stacked metal structure of Ti/TiN/Al.
However, if the Ti layer is deposited on the bottom of the via hole as described above, the residual polarization characteristics of the ferroelectric capacitor may still be deteriorated during a subsequent high temperature thermal treatment process following the formation of the capacitor. This is thought to be caused by defects in the perovskite structure of the ferroelectric film due to the diffusion of Ti through Pt. To solve the problem caused by Ti diffusion, there has been proposed a method of using only Al to form the second metal interconnection without using the Ti/TiN layer. However, as described above, Al also reacts with Pt during the thermal treatment process and deteriorates the polarization characteristics of the ferroelectric capacitor.
To solve the above-mentioned problem of Ti diffusion, there has been proposed another method of using aluminum (Al) and only a TiN layer as a barrier layer, without using a Ti layer as an ohmic layer in forming a second metal interconnection. According to this method, the polarization characteristics of a ferroelectric capacitor are maintained. However, this method has a drawback because via contact resistance is typically increased when the Ti ohmic layer is omitted.
Thus, according to currently developed metal interconnection technologies, it is quite difficult to maintain the polarization characteristics of ferroelectric capacitors in cell array regions and also improve contact resistance in peripheral circuit regions.